1. Field of the Invention
The present invention relates to a control signal generation circuit, and more particularly to a favorable structure of the control signal generation circuit for generating an internal control signal of a semiconductor device.
2. Description of the Background Art
In semiconductor devices including memory devices, generally a circuit supplying a control signal as an output is provided for the generation of an internal control signal which is employed for the control of a series of internal operations sequentially performed at a predetermined timing.
In a control signal generation circuit in a DRAM (Dynamic Random Access Memory), for example, first, command control signals such as /RAS, /CAS and /WE signals are supplied from an external source, then a command is generated according to the combination thereof, and a plurality of internal control signals are sequentially activated for carrying out a series of operations corresponding to the command.
FIG. 14 is a circuit diagram showing a structure of a control signal generation circuit 510 which is an example of a control circuit for generating a read command in the DRAM.
With reference to FIG. 14, control signal generation circuit 510 includes a logic gate LG50 supplying the result of an AND operation as an output according to the combination of signal levels of command control signals such as /RAS, /CAS, and so on supplied as inputs, a logic gate LG52 supplying the result of an OR operation of the output results from logic gates LG50 and LG54, and an edge trigger flip flop 515 taking in the output of logic gate LG52 in response to the rising edge of a clock signal CLK and determining the signal level of a read command signal READ.
Read command signal READ is activated (to an H level) when the read command is designated. A burst operation end signal /BSTEND is a signal which is set to an H level at the start of the reading operation and set to an L level at the end of the burst operation. Logic gate LG54 supplies the result of the AND operation of read command signal READ and burst operation end signal /BSTEND as an output. Thus the output of logic gate LG54 is set to an H level at the start of the reading operation and maintained at an H level until the end of the burst operation.
Therefore, when the read command is designated by the combination of command control signals supplied as inputs to logic gate LG50, read command signal READ is set to an H level by flip flop 515 at the rise of clock signal CLK.
After the reading operation is started, the output of logic gate LG54 is turned to an L level in response to the end of the burst operation. Through taking in the L level output via logic gate LG52 from LG54 at the rising edge of clock signal CLK, flip flop 515 resets read command signal READ to an L level.
Logic gate LG50 receives a row address strobe signal /RAS, a column address strobe signal /CAS, a chip select signal /CS and a write enable signal /WE. The combination of L level /CAS and /CS signals and H level /RAS and /WE signals designates the read command and causes the output of logic gate LG50 to be set to an H level.
In response to the activation of read command signal READ supplied as an output from control signal generation circuit 510, various internal control signals are activated to carry out the operation according to the read command. As an example, the generation of internal control signals for a column-related reading operation of the DRAM will be described below.
FIG. 15 is a circuit diagram showing a structure of a control signal generation circuit 520 supplying as an output a preamplifier activation signal PAE, which is one of internal control signals relating to the column-related reading operation.
With reference to FIG. 15, control signal generation circuit 520 includes a delay circuit 522 receiving clock signal CLK and supplying clock signal CLK delayed by a delay time td0 as an output, a logic gate LG60 supplying the result of an AND operation of read command signal READ and the output of delay circuit 522, a delay circuit 524 delaying the output of logic gate LG60 (by a delay time td1), a delay circuit 526 delaying the output of delay circuit 524 (by a delay time td2) and a logic gate LG62 carrying out an AND operation of the outputs of delay circuits 524 and 526. Logic gate LG62 supplies preamplifier activation signal PAE as an output.
FIG. 16 is a circuit diagram showing a structure of a control signal generation circuit 530 generating a column decoder activation signal CDE, which is one of the control signals relating to the column-related reading operation like the preamplifier activation signal.
With reference to FIG. 16, control signal generation circuit 530 supplies column decoder activation signal CDE according to read command signal READ and clock signal CLK, similarly to control signal generation circuit 520.
Though control signal generation circuit 530 has a similar structure to control signal generation circuit 520, differences exist in that delay circuits 522, 524 and 526 in control signal generation circuit 520 are replaced with delay circuits 532, 534 and 536 for adding different delay times td3, td4 and td5, respectively, in control signal generation circuit 530, and that control signal generation circuit 530 includes an OR gate as a logic gate LG66 for supplying control signal CDE as an output.
The activation and inactivation of internal control signals, including PAE and CDE are required to be carried out at appropriate timing for the correct reading operation. The timing is adjusted through the suitable setting of delay time added by a group of delay circuits to a reference control signal, which is obtained as the result of AND operation of read command signal READ and the signal obtained by delaying clock signal CLK.
FIG. 17 is a timing chart referenced for describing operations of control signal generation circuits 520 and 530.
As shown in FIG. 17, when the read command is designated according to the combination of command control signals /RAS, /CAS, /CS and /WE, the read command is taken in at the time of the rise of clock signal CLK at time t0. At time td1, that is, tdR after time t0, read command signal READ is activated (to an H level) by control signal generation circuit 510.
When the sum of delay time added by delay circuit 522 to clock signal CLK and delay time added by delay circuits 524 and 526 to the output of logic gate LG60, that is, td0+td1+td2, has passed after time t0, preamplifier activation signal PAE is activated (to an H level) at time t3. On the other hand, the fall of clock signal CLK is transmitted to logic gate LG62 after the time delay td0+td1. Hence, provided that the activation period of clock signal CLK is Tw, preamplifier activation signal PAE is maintained at an active state (H level) for the duration of Twxe2x88x92td2 and then attains an inactive state (L level) at time t4.
Column decoder activation signal CDE is activated (to an H level) in response to the rise of clock signal CLK at time t2, that is, the sum of delay time added at delay circuits 532 and 534, td3+td4, has elapsed after time t0.
The falling edge of clock signal CLK is transmitted to logic gate LG66 via delay circuits 532 and 534 in a similar manner. As delay time td5 is further added to one input to logic gate LG66 by delay circuit 536, column decoder activation signal CDE is maintained at an active state for the duration of Tw+td5 and inactivated (to an L level) again at time t5.
Thereafter, while read command signal READ is in an active state, the activation and inactivation of these control signals are carried out at the timing as described above in response to the rising and falling edges of clock signal CLK.
In control signal generation circuits 510 and 520, through the suitable setting of delay times td0xcx9ctd5, column decoder activation signal CDE is activated after the completion of taking-in and decoding of column address following the start of reading operation and the preamplifier signal is activated after read data appears on a data line in response to the activation of column decoder activation signal CDE. On the other hand, for the inactivation of the column-related reading operation, column decoder activation signal CDE is inactivated following the inactivation of the preamplifier signal.
Here, delay times td0 and td3 added respectively by delay circuits 522 and 532 are set such that they are longer than time tdR, that is, a period from the rise of clock signal CLK to the activation of read command signal READ. The purpose is to prevent an activation period of a control signal generated in response to a rising edge of a clock signal at the command generation from being shortened than that of a signal generated in response to other rising edge of the clock signal.
As shown in FIGS. 15 and 16, the delay circuits for the timing adjustment have generally been arranged independently for internal control signals of different types in the conventional control signal generation circuit. As a result, however, the increase in the number of types of internal control signals directly leads to increase in the number of delay circuits hence to the increase in layout area. The reduction of layout are is crucial today as the reduction in size of devices to which semiconductor device is incorporated is being advanced.
An object of the present invention is to reduce the layout area of the control signal generation circuit by sharing a delay circuit among a plurality of control signal generation circuits.
Another object of the present invention is to reduce the chip area of a semiconductor device by providing a plurality of control signal generation circuits sharing a delay circuit.
The present invention is, in brief, a control signal generation circuit generating a plurality of first control signals according to a second control signal which serves as a reference and including a delay circuit and a plurality of signal generation circuits.
The delay circuit has a function of delaying the second control signal by a predetermined time period and includes a plurality of delay units connected in series and a plurality of taps taking out output signals from the plurality of delay units, respectively. The plurality of signal generation circuits generate the plurality of first control signals, respectively. Each of the plurality of signal generation circuits sets a signal level of corresponding one of the plurality of first control signals according to the signal levels of at least two of a plurality of delay signals supplied to the plurality of taps, respectively.
According to another aspect, the present invention is a semiconductor device including a control signal generation circuit.
The control signal generation circuit generates a plurality of internal control signals for carrying out a series of predetermined operations in the semiconductor device according to a control signal which serves as a reference and includes a delay circuit for delaying the control signal as a reference by a predetermined time period. The delay circuit includes a plurality of delay units connected in series and a plurality of taps for taking out output signals of the plurality of delay units, respectively.
The control signal generation circuit further includes a plurality of signal generation circuits for supplying a plurality of internal control signals, respectively. Each of the plurality of signal generation circuits sets a signal level of corresponding one of the plurality of control signals according to the signal levels of at least two of the plurality of delay signals supplied as outputs to the plurality of taps, respectively.
According to still another aspect, the present invention is a control signal generation circuit generating a plurality of first control signals based on a second control signal having a first state and a second state, and the control signal generation circuit includes a first delay circuit, a second delay circuit, and a plurality of signal generation circuits.
The first delay circuit is responsive to a first transition of the second control signal from the first state to the second state to output a plurality of first delay signals. A signal level of each of the plurality of first delay signals is changed a delay time after the first transition. The delay time is different from signal to signal. The second delay circuit is responsive to a second transition of the second control signal from the second state to the first state to output a plurality of second delay signals. A signal level of each of the plurality of second delay signals is changed a delay time after the second transition. The delay time is different from signal to signal.
The plurality of signal generation circuits generate the plurality of first control signals, respectively. Each of the signal generation circuits sets a signal level of a corresponding one of the plurality of first control signals in response to change in signal levels of the plurality of first delay signals and the plurality of second delay signals.
According to still another aspect, the present invention is a semiconductor device including a control signal generation circuit.
The control signal generation circuit is responsive to a reference control signal having a first state and a second state to generate a plurality of internal control signals for performing a series of predetermined operations in the semiconductor device. The control signal generation circuit includes a first delay circuit responsive to a first transition of the reference control signal from the first state to the second state to output a plurality of first delay signals. A signal level of each of the plurality of first delay signals is changed a delay time after the first transition. The delay time is different from signal to signal. The control signal generation circuit further includes a second delay circuit responsive to a second transition of the reference control signal from the second state to the first state to output a plurality of second delay signals. A signal level of each of the plurality of second delay signals is changed a delay time after the second transition. The delay time is different from signal to signal. The control signal generation circuit further includes a plurality of signal generation circuits to generate the plurality of internal control signals, respectively. Each of the signal generation circuits sets a signal level of a corresponding one of the plurality of internal control signals in response to change in signal levels of the plurality of first delay signals and the plurality of second delay signals.
Thus, a main advantage of the present invention lies in that as the plurality of second control signals can be generated based on the first control signal which is delayed by the predetermined time period by the delay circuit shared among signal generation circuits, the layout area of the control signal generation circuit generating the plurality of internal control signals at a predetermined timing according to the same control signal can be reduced.
In addition, the layout area of the semiconductor device can be reduced as the internal control signal controlling the operation of the semiconductor device is generated by the control signal generation circuit capable of generating the internal control signal according to the reference control signal which is delayed by a predetermined time period by the delay circuit shared among the signal generation circuits.
Further, the plurality of first control signals which are generated in response to rise and fall of the second control signal serving as a reference can be generated through the common delay circuit without increase in layout area of the control signal generation circuit and hence, the semiconductor device. Still further, the timing accuracy of the first control signal can be improved because the delay circuit is shared and the device becomes less susceptible to the effect of variation in delay time caused by the difference in layout.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.